The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2019

Filed:

Mar. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jeremy D. Ecton, Gilbert, AZ (US);

Changhua Liu, Chandler, AZ (US);

Arnab Roy, Chandler, AZ (US);

Oscar U. Ojeda, Chandler, AZ (US);

Timothy A. White, Chandler, AZ (US);

Nicholas S. Haehn, Scottsdale, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3213 (2006.01); H05K 3/06 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/32134 (2013.01); H01L 21/32139 (2013.01); H05K 3/067 (2013.01); H01L 21/6708 (2013.01);
Abstract

The systems and methods described herein use at least one etchant and at least one photochemically active material in conjunction with electromagnetic energy applied simultaneous with the etchant and photochemically active material during the etching process. The interaction between the electromagnetic energy and the photochemically active material preferentially increases the etch rate in a direction along the axis of incidence of the electromagnetic energy, thereby permitting the anisotropic formation of voids within the semiconductor substrate. These anisotropic voids may be more closely spaced (i.e., arranged on a tighter pitch) than the isotropic voids produced using conventional etching technologies. By placing the voids in the semiconductor substrate on a tighter pitch, greater component density may be achieved.


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