The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2019

Filed:

Nov. 06, 2018
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Jaynal A. Molla, Gilbert, AZ (US);

Lakshminarayan Viswanathan, Phoenix, AZ (US);

Geoffrey Tucker, Tempe, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 23/40 (2006.01); H01L 23/36 (2006.01); H01L 23/367 (2006.01); H01L 23/427 (2006.01); H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02109 (2013.01); H01L 21/02304 (2013.01); H01L 21/02697 (2013.01); H01L 23/36 (2013.01); H01L 23/3677 (2013.01); H01L 23/40 (2013.01); H01L 23/427 (2013.01); H01L 2021/6027 (2013.01);
Abstract

Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.


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