The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Jan. 07, 2016
Applicant:

Shin-etsu Handotai Co., Ltd., Tokyo, JP;

Inventors:

Toru Ishizuka, Takasaki, JP;

Norihiro Kobayashi, Takasaki, JP;

Masatake Nakano, Annaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 21/304 (2006.01); H01L 21/321 (2006.01); H01L 21/762 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/304 (2013.01); H01L 21/02 (2013.01); H01L 21/02008 (2013.01); H01L 21/02013 (2013.01); H01L 21/02019 (2013.01); H01L 21/02104 (2013.01); H01L 21/02107 (2013.01); H01L 21/02499 (2013.01); H01L 21/02595 (2013.01); H01L 21/0445 (2013.01); H01L 21/76254 (2013.01); H01L 27/12 (2013.01); H01L 27/1203 (2013.01); H01L 21/02024 (2013.01); H01L 21/3212 (2013.01);
Abstract

Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.


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