The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2019

Filed:

Oct. 30, 2017
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Bernhard Grote, Phoenix, AZ (US);

Xin Lin, Phoenix, AZ (US);

Saumitra Raj Mehrotra, Scottsdale, AZ (US);

Ljubo Radic, Gilbert, AZ (US);

Ronghua Zhu, Chandler, AZ (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/761 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/36 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7823 (2013.01); H01L 21/26513 (2013.01); H01L 21/761 (2013.01); H01L 29/063 (2013.01); H01L 29/0634 (2013.01); H01L 29/0646 (2013.01); H01L 29/0696 (2013.01); H01L 29/1083 (2013.01); H01L 29/36 (2013.01); H01L 29/66681 (2013.01); H01L 29/7835 (2013.01); H01L 29/0653 (2013.01); H01L 29/0869 (2013.01); H01L 29/0886 (2013.01); H01L 29/402 (2013.01); H01L 29/4916 (2013.01);
Abstract

An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.


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