The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2019

Filed:

Dec. 06, 2017
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Carsten Schaeffer, Annenheim, AT;

Andreas Moser, Maria-Rain, AT;

Matthias Kuenle, Villach, AT;

Matteo Dainese, Villach, AT;

Roland Rupp, Lauf, DE;

Hans-Joachim Schulze, Taufkirchen, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/308 (2006.01); H01L 29/739 (2006.01); H01L 21/8234 (2006.01); H01L 27/12 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76248 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02595 (2013.01); H01L 21/02647 (2013.01); H01L 21/02667 (2013.01); H01L 21/26513 (2013.01); H01L 21/3065 (2013.01); H01L 21/3083 (2013.01); H01L 21/30604 (2013.01); H01L 21/30625 (2013.01); H01L 21/762 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 27/1207 (2013.01); H01L 29/06 (2013.01); H01L 29/0649 (2013.01); H01L 29/08 (2013.01); H01L 29/0804 (2013.01); H01L 29/0865 (2013.01); H01L 29/0882 (2013.01); H01L 29/10 (2013.01); H01L 29/1095 (2013.01); H01L 29/66 (2013.01); H01L 29/66333 (2013.01); H01L 29/66348 (2013.01); H01L 29/66712 (2013.01); H01L 29/66734 (2013.01); H01L 29/7393 (2013.01); H01L 29/7812 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 27/088 (2013.01); H01L 29/7395 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.


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