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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10403580 B1

PDFFull Text
Date of Patent:
Sep. 03, 2019

Filed:

Dec. 29, 2017

Molded substrate package in fan-out wafer level package

Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Lizabeth Keser, Munich, DE;

Thomas Ort, Veitsbronn, DE;

Thomas Wagner, Regelsbach, DE;

Bernd Waidhas, Pettendorf, DE;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:

Schwegman Lundberg & Woessner, P.A.

Primary Examiner:

Mamadou L Diallo

Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 21/481 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49833 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/224 (2013.01); H01L 2924/15172 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/18161 (2013.01);
Abstract

An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die. A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

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