The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2019
Filed:
Sep. 13, 2016
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Fong-Yuan Chang, Hsinchu County, TW;
Lee-Chung Lu, Taipei, TW;
Yi-Kan Cheng, Taipei, TW;
Sheng-Hsiung Chen, Hsinchu County, TW;
Po-Hsiang Huang, Tainan, TW;
Shun Li Chen, Tainan, TW;
Jeo-Yen Lee, Taipei, TW;
Jyun-Hao Chang, Kaohsiung, TW;
Shao-Huan Wang, Taichung, TW;
Chien-Ying Chen, Chiayi, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Abstract
In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.