The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Jan. 11, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Judson R. Holt, Ballston Lake, NY (US);

George Mulfinger, Wilton, NY (US);

Timothy J. McArdle, Ballston Lake, NY (US);

Thomas Merbeth, Dresden, DE;

Ömür Aydin, Dresden, DE;

Ruilong Xie, Niskayuna, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 27/11 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/82385 (2013.01); H01L 21/823456 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 27/1104 (2013.01); H01L 29/41775 (2013.01); H01L 29/66515 (2013.01);
Abstract

One illustrative method disclosed herein includes, among other things, performing at least one etching process to expose at least a portion of an upper surface of a gate electrode of a first transistor device and at least a vertical portion of one side surface of the gate electrode and performing a material growth process to form a conductive gate-to-source/drain (GSD) contact structure that conductively couples the gate electrode of the first transistor device to a source/drain region of the first transistor device, wherein the conductive GSD contact structure comprises a non-single crystal material portion positioned on previously exposed portions of the gate electrode and a single crystal material portion positioned in the source/drain region.


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