The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2019
Filed:
Nov. 14, 2017
Globalfoundries Inc., Grand Cayman, KY;
Yongiun Shi, Clifton Park, NY (US);
Lei Sun, Altamont, NY (US);
Laertis Economikos, Wappingers Falls, NY (US);
Ruilong Xie, Schenectady, NY (US);
Lars Liebmann, Mechanicville, NY (US);
Chanro Park, Clifton Park, NY (US);
Daniel Chanemougame, Niskayuna, NY (US);
Min Gyu Sung, Latham, NY (US);
Hsien-Ching Lo, Clifton Park, NY (US);
Haiting Wang, Clifton Park, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.