The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Sep. 11, 2017
Applicant:
Silicon Storage Technology, Inc., San Jose, CA (US);
Inventors:
Assignee:
Silicon Storage Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11531 (2017.01); H01L 27/11524 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11531 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 29/42328 (2013.01); H01L 29/66484 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract
A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.