The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2019
Filed:
Jul. 16, 2018
United Microelectronics Corp., Hsin-Chu, TW;
Chih-Hsiang Chang, Tainan, TW;
Hou-Jen Chiu, Taichung, TW;
Mei-Ling Chao, Tainan, TW;
Tien-Hao Tang, Hsinchu, TW;
Kuan-Cheng Su, Taipei, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An Ndrain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The Ndrain doping region is contiguous with a bottom edge of the first spacer. An Nsource doping region is disposed in the P-type substrate opposite to the Ndrain doping region. The Nsource doping region is kept a predetermined distance from a bottom edge of the second spacer. A Ppick-up ring is disposed in the P-well region and surrounds the gate finger, the Ndrain doping region, and the Nsource doping region.