The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2019
Filed:
Sep. 24, 2014
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Kimin Jun, Hillsboro, OR (US);
Patrick Morrow, Portland, OR (US);
Donald Nelson, Beaverton, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 21/3081 (2013.01); H01L 21/76802 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/0676 (2013.01);
Abstract
A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.
Quick Actions:
Jun, Kimin. (2019). Vertical channel transistors fabrication process by selective subtraction of a regular grid (U.S. Patent No. 10361090). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10361090
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile