The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Dec. 27, 2017
Applicant:

Spin Transfer Technologies, Inc., Fremont, CA (US);

Inventors:

Neal Berger, Cupertino, CA (US);

Benjamin Louie, Fremont, CA (US);

Mourad El-Baraji, Fremont, CA (US);

Lester Crudele, Tomball, TX (US);

Daniel Hillman, San Jose, CA (US);

Assignee:

Spin Memory, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/16 (2006.01); G06F 12/0804 (2016.01); G11C 7/20 (2006.01); G11C 7/10 (2006.01); G11C 14/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G06F 12/0804 (2013.01); G11C 7/1039 (2013.01); G11C 7/20 (2013.01); G11C 11/1653 (2013.01); G11C 11/1673 (2013.01); G11C 11/1677 (2013.01); G11C 11/1697 (2013.01); G11C 13/0033 (2013.01); G11C 14/0081 (2013.01);
Abstract

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words and associated memory addresses into a cache memory, and wherein each data word of the second plurality of data words is associated with a pending operation. Additionally, the method comprises detecting a power up signal and responsive to the power up signal, transferring the second plurality of data words and associated memory addresses from the secure memory storage area to the cache memory. Finally, responsive to the transferring, and before the memory device is powered up, the method comprises processing the second plurality of data words and associated memory addresses from the cache memory to the pipeline for writing data to the memory bank during power up.


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