The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Oct. 27, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Yi Qi, Niskayuna, NY (US);

Sang Woo Lim, Ballston Spa, NY (US);

Kyung-Bum Koo, Albany, NY (US);

Alina Vinslava, Ballston Lake, NY (US);

Pei Zhao, Clifton Park, NY (US);

Zhenyu Hu, Clifton Park, NY (US);

Hsien-Ching Lo, Clifton Park, NY (US);

Joseph F. Shepard, Jr., Poughkeepsie, NY (US);

Shesh Mani Pandey, Saratoga Springs, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 21/3065 (2006.01); H01L 29/78 (2006.01); H01L 29/161 (2006.01); H01L 29/16 (2006.01); H01L 29/165 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66636 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 21/845 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/66795 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract

Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.


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