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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10355020 B1

PDFFull Text
Date of Patent:
Jul. 16, 2019

Filed:

Jun. 13, 2016

Finfets having strained channels, and methods of fabricating finfets having strained channels

Applicants:

International Business Machines Corporation, Armonk, NY (US);

Globalfoundries Inc., Grand Cayman, KY;

Stmicroelectronics, Inc., Coppell, TX (US);

Inventors:

Qing Liu, Watervliet, NY (US);

Xiuyu Cai, Niskayuna, NY (US);

Ruilong Xie, Schenectady, NY (US);

Chun-chen Yeh, Clifton Park, NY (US);

Assignees:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

STMICROELECTRONICS, INC., Coppell, TX (US);

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:

Scully, Scott, Murphy & Presser, P.C.

Steven J. Meyers

Primary Examiner:

Sophia T Nguyen

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01); G06N 3/04 (2006.01); G10L 15/16 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1211 (2013.01); G06N 3/04 (2013.01); G10L 15/16 (2013.01); H01L 21/28132 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/41775 (2013.01); H01L 29/41783 (2013.01); H01L 29/41791 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/365 (2013.01); H01L 2029/7858 (2013.01); H01L 2924/13067 (2013.01);
Abstract

Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

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