The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2019

Filed:

Dec. 27, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Fu-Ting Sung, Taoyuan, TW;

Chung-Chiang Min, Hsinchu County, TW;

Wei-Hang Huang, Kaohsiung, TW;

Shih-Chang Liu, Kaohsiung County, TW;

Chia-Shiung Tsai, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/34 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 27/11521 (2017.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/76805 (2013.01); H01L 23/528 (2013.01); H01L 27/11521 (2013.01); H01L 29/34 (2013.01); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01); H01L 29/4916 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 29/7831 (2013.01); H01L 29/7881 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a control gate over a substrate and forming a dielectric layer covering the control gate. The method further includes forming a conductive layer having a first portion and a second portion over the dielectric layer. In addition, the first portion of the conductive layer is separated from the control gate by the dielectric layer. The method further includes forming an oxide layer on a top surface of the first portion of the conductive layer and removing the second portion of the conductive layer to form a memory gate.


Find Patent Forward Citations

Loading…