The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Dec. 21, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Naohiro Hosoda, Yokkaichi, JP;

Keisuke Shigemura, Yokkaichi, JP;

Junichi Ariyoshi, Yokkaichi, JP;

Kazuki Kajitani, Yokkaichi, JP;

Yuji Fukano, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11556 (2017.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 27/11524 (2017.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 29/408 (2013.01);
Abstract

A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.


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