The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2019

Filed:

Nov. 13, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Peter Baars, Dresden, DE;

Rick Carter, Saratoga Springs, NY (US);

Vikrant Chauhan, Cohoes, NY (US);

George Jonathan Kluth, Saratoga Springs, NY (US);

Anurag Mittal, San Jose, CA (US);

David Pritchard, Glenville, NY (US);

Mahbub Rashed, Cupertino, CA (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/417 (2006.01); H01L 27/12 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823871 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 27/0922 (2013.01); H01L 27/1207 (2013.01); H01L 29/41783 (2013.01); H01L 29/4941 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.


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