The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Dec. 19, 2017
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Tsong-Lin Shen, Kaohsiung, TW;

Chen-Hsiao Wang, Hsinchu, TW;

Sheng-Wei Hung, Taipei, TW;

Chin-Tsai Chang, Tainan, TW;

Hui-Lung Chou, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/528 (2013.01); H01L 23/5329 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A semiconductor chip is provided. The semiconductor chip includes at least one interlayer dielectric layer, a transmission pattern and a stress absorption structure. The at least one interlayer dielectric layer is disposed on a substrate. The transmission pattern is disposed on the at least one interlayer dielectric layer and within a peripheral region of the semiconductor chip. The transmission pattern is electrically connected to an external signal source. The stress absorption structure is disposed in the at least one interlayer dielectric layer within the peripheral region, and electrically connected to the transmission pattern. The stress absorption structure is covered by the transmission pattern.


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