The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Nov. 24, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Hao Lu, Taoyuan, TW;

Yi-Fang Pai, Hsinchu, TW;

Tuoh-Bin Ng, Hsinchu, TW;

Li-Li Su, Zhubei, TW;

Chii-Horng Li, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 29/167 (2006.01); H01L 29/45 (2006.01); H01L 21/02 (2006.01); H01L 23/535 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823418 (2013.01); H01L 21/02532 (2013.01); H01L 21/02573 (2013.01); H01L 21/02609 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 23/535 (2013.01); H01L 27/0886 (2013.01); H01L 29/045 (2013.01); H01L 29/0847 (2013.01); H01L 29/167 (2013.01); H01L 29/45 (2013.01); H01L 29/7848 (2013.01);
Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.


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