The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Nov. 10, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Sheng-Hsiang Chiu, Tainan, TW;

Meng-Tse Chen, Changzhi Township, TW;

Ching-Hua Hsieh, Hsinchu, TW;

Chung-Shi Liu, Hsinchu, TW;

Sheng-Feng Weng, Taichung, TW;

Ming-Da Cheng, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 25/065 (2006.01); H01L 21/3105 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01); H01L 25/03 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/31053 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 21/76877 (2013.01); H01L 21/78 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5389 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/03 (2013.01); H01L 25/50 (2013.01); H01L 21/486 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/03002 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/11002 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2924/1531 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound layer, forming a plurality of vias over the plurality of contact pads, attaching a semiconductor die on the first molding compound layer, depositing a second molding compound layer over the carrier, wherein the semiconductor die and the plurality of vias are embedded in the second molding compound layer, forming an interconnect structure over the second molding compound layer and forming a plurality of bumps over the interconnect structure.


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