The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2019
Filed:
Dec. 08, 2017
Intel Corporation, Santa Clara, CA (US);
Richard Fastow, Cupertino, CA (US);
Xin Sun, Fremont, CA (US);
Uday Chandrasekhar, Santa Clara, CA (US);
Krishna K. Parat, Palo Alto, CA (US);
Camila Jaramillo, San Jose, CA (US);
Purval S. Sule, Folsom, CA (US);
Aliasgar S. Madraswala, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.