The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2019

Filed:

Nov. 01, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Weiming Chris Chen, Taipei, TW;

Ting-Yu Yeh, Hsinchu, TW;

Chia-Hsin Chen, Tainan, TW;

Tu-Hao Yu, Hsin-Chu, TW;

Kuo-Chiang Ting, Hsinchu, TW;

Shang-Yun Hou, Hsinchu, TW;

Chi-Hsi Wu, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 21/00 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/3142 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/50 (2013.01); H01L 25/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor structure includes a first substrate including a first surface and a second surface opposite to the first surface; a first die disposed over the second surface of the first substrate; a plurality of first conductive bumps disposed between the first die and the first substrate; a molding disposed over the first substrate and surrounding the first die and the plurality of first conductive bumps; a second substrate disposed below the first surface of the first substrate; a plurality of second conductive bumps disposed between the first substrate and the second substrate; and a second die disposed between the first substrate and the second substrate.


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