The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2019
Filed:
Jan. 08, 2018
Applicant:
Nxp Usa, Inc., Austin, TX (US);
Inventors:
Jean-Philippe Laine, Saint Lys, FR;
Jiang-kai Zuo, Chandler, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Patrice Besse, Tournefeuille, FR;
Rouying Zhan, Chandler, AZ (US);
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/50 (2006.01); H01L 27/02 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H02H 9/04 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0277 (2013.01); H01L 23/50 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/36 (2013.01); H01L 29/42372 (2013.01); H01L 29/6656 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01); H02H 9/046 (2013.01);
Abstract
The present disclosure teaches a Field-Effect Transistor (FET) configured as a diode to provide ESD protection. The field-effect transistor has its gate, source, and body connected to a common power supply rail. A low-density doped drain region extends in a length direction beyond the gate sidewall spacers of the transistor to provide a lower leakage current than would otherwise be exhibited by the protection device.