The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Aug. 18, 2014
Applicants:

Stmicroelectronics, Inc., Coppell, TX (US);

International Business Machines Corporation, Armonk, NY (US);

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Qing Liu, Watervliet, NY (US);

Chun-chen Yeh, Clifton Park, NY (US);

Ruilong Xie, Schenectady, NY (US);

Xiuyu Cai, Niskayuna, NY (US);

Assignees:

STMICROELECTRONICS, INC., Coppell, TX (US);

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/167 (2006.01); H01L 29/161 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/26513 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 29/0653 (2013.01); H01L 29/1083 (2013.01); H01L 29/161 (2013.01); H01L 29/167 (2013.01); H01L 21/823892 (2013.01);
Abstract

A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region.


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