The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2019

Filed:

Dec. 22, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yan A. Borodovsky, Portland, OR (US);

Donald W. Nelson, Beaverton, OR (US);

Mark C. Phillips, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 9/00 (2006.01); H01L 21/68 (2006.01); H01L 21/027 (2006.01); H01J 37/317 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/682 (2013.01); G03F 9/00 (2013.01); H01J 37/3174 (2013.01); H01L 21/0277 (2013.01); H01L 21/31144 (2013.01);
Abstract

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of real-time alignment of a wafer situated on a stage of an e-beam tool involves collecting backscattered electrons from an underlying patterned feature of the wafer while an e-beam column of the e-beam tool writes during scanning of the stage. The collecting is performed by an electron detector placed at the e-beam column bottom. The method also involves performing linear corrections of an alignment of the stage relative to the e-beam column based on the collecting.


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