The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2019
Filed:
Jun. 08, 2017
Applicant:
Sandisk Semiconductor (Shanghai) Co., Ltd., Shanghai, CN;
Inventors:
Junrong Yan, Shanghai, CN;
Xiaofeng Di, Shanghai, CN;
Chee Keong Chin, Shanghai, CN;
Kim Lee Bock, Shanghai, CN;
Mingxia Wu, Shanghai, CN;
Assignee:
SanDisk Semiconductor (Shanghai) Co. Ltd., Shanghai, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/304 (2006.01); H01L 21/288 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/288 (2013.01); H01L 21/304 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 25/50 (2013.01); H01L 24/17 (2013.01); H01L 24/43 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06179 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16013 (2013.01); H01L 2224/16014 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17179 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48463 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/20104 (2013.01);
Abstract
A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.