The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2019
Filed:
Jan. 20, 2017
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Yun-Lin Wu, Hsin-Chu, TW;
Cheng-Cheng Kuo, Hsinchu, TW;
Chia-Ping Chiang, Taipei, TW;
Chih-Wei Hsu, Zhubei, TW;
Hua-Tai Lin, Hsinchu, TW;
Kuei-Shun Chen, Hsinchu, TW;
Yuan-Hsiang Lung, Hsinchu, TW;
Yan-Tso Tsai, Hsin-Chu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsin-Chu, TW;
Abstract
A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.