The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Dec. 27, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Wan-Yu Lee, Taipei, TW;

Chun-Hao Tseng, Taichung, TW;

Jui Hsieh Lai, Taoyuan, TW;

Tien-Yu Huang, Shuishang Township, TW;

Ying-Hao Kuo, Hsinchu, TW;

Kuo-Chung Yee, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 21/50 (2006.01); H01L 31/0232 (2014.01); H01L 31/09 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 31/0203 (2014.01); H01L 33/52 (2010.01); H01L 33/48 (2010.01); H01L 23/28 (2006.01); H01L 23/485 (2006.01); H01L 23/00 (2006.01); H01L 27/146 (2006.01); H01L 21/311 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/29 (2006.01); H01L 25/16 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3192 (2013.01); H01L 21/31111 (2013.01); H01L 21/481 (2013.01); H01L 21/4857 (2013.01); H01L 21/50 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6836 (2013.01); H01L 21/76838 (2013.01); H01L 23/28 (2013.01); H01L 23/293 (2013.01); H01L 23/31 (2013.01); H01L 23/3107 (2013.01); H01L 23/3114 (2013.01); H01L 23/3171 (2013.01); H01L 23/48 (2013.01); H01L 23/485 (2013.01); H01L 23/538 (2013.01); H01L 23/5383 (2013.01); H01L 23/5389 (2013.01); H01L 24/06 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/167 (2013.01); H01L 25/50 (2013.01); H01L 27/14618 (2013.01); H01L 31/0203 (2013.01); H01L 31/0232 (2013.01); H01L 31/09 (2013.01); H01L 33/48 (2013.01); H01L 33/52 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24195 (2013.01); H01L 2924/1032 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13091 (2013.01);
Abstract

In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.


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