The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
May. 10, 2018
United Microelectronics Corp., Hsin-Chu, TW;
Wei-Chi Lee, Tainan, TW;
Han-Tsun Wang, Tainan, TW;
Chang-Hung Chen, Tainan, TW;
Po-Yu Yang, Hsinchu, TW;
Mei-Ying Fan, Hsinchu County, TW;
Mu-Kai Tsai, Hsinchu County, TW;
Guan-Shyan Lin, Taipei, TW;
Tsz-Hui Kuo, Hsinchu, TW;
Cheng-Hsiung Chen, Taipei, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.