The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2019
Filed:
Apr. 22, 2016
Shanghai Micro Electronics Equipment (Group) Co., Ltd., Shanghai, CN;
Gang Wang, Shanghai, CN;
Yunbin Pu, Shanghai, CN;
Shaoyu Wang, Shanghai, CN;
Jiaozeng Zheng, Shanghai, CN;
Jie Jiang, Shanghai, CN;
SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD., Shanghai, CN;
Abstract
An apparatus for pre-aligning a wafer comprises: a wafer stage for carrying the wafer, wherein a first alignment mark (W1) and a second alignment mark (W2) are arranged on the wafer such that they are substantially symmetrical to each other with respect to a center of the wafer; a peripheral vision acquisition system (), configured to perform a first positional compensation for the wafer based on a relative positional relationship of an edge or a notch of the wafer with respect to the wafer stage; and a mark detection system (), configured to capture images of the first and second alignment marks (W1, W2) and perform a second positional compensation for the wafer by determining a relative positional relationship of the center of the wafer with respect to a center of the wafer stage based on the positions of the first and second alignment marks (W1, W2) in a coordinate system of the mark detection system, wherein the coordinate system of the mark detection system () has a horizontal axis (X) defined by a line passing through the center of the wafer stage and a center of the mark detection system () and a vertical axis (Y) defined by a line crossing the horizontal axis (X) at right angles and passing through the center of the wafer stage.