The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Jan. 06, 2017
Varian Semiconductor Equipment Associates, Inc., Gloucester, MA (US);
Morgan D. Evans, Manchester, MA (US);
Tristan Ma, Lexington, MA (US);
Kevin Anglin, Somerville, MA (US);
Motoya Okazaki, San Jose, CA (US);
Johannes M. van Meer, Middleton, MA (US);
VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC., Gloucester, MA (US);
Abstract
An apparatus of a wafer processing apparatus includes at least one memory and logic, at least a portion of which is implemented in circuitry of the wafer processing apparatus including at least one processor coupled to the at least one memory. The logic may provide a 3D model of a surface of a wafer, the wafer defining a wafer plane; and modify a surface feature in a Z-direction along the surface of the wafer based on at least one of: an X-critical dimension (CD) extending along an X-direction of the wafer plane, and a Y-CD extending along a Y direction of the wafer plane.