The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Jul. 12, 2017
Applied Materials, Inc., Santa Clara, CA (US);
Keith Tatseun Wong, Los Gatos, CA (US);
Shiyu Sun, Santa Clara, CA (US);
Sean S. Kang, San Ramon, CA (US);
Nam Sung Kim, Sunnyvale, CA (US);
Srinivas D. Nemani, Sunnyvale, CA (US);
Ellie Y. Yieh, San Jose, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, maintaining a process pressure at greater than 5 bar, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.