The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Jan. 14, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chun Hsiung Tsai, Hsinchu County, TW;

Yuan-Ko Hwang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/04 (2006.01); H01L 21/3065 (2006.01); H01L 29/16 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02447 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/02639 (2013.01); H01L 29/165 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01); H01L 29/7834 (2013.01);
Abstract

The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer.


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