The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Feb. 08, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Hideaki Kawahara, Plano, TX (US);

Christopher Boguslaw Kocon, Mountain Top, PA (US);

Seetharaman Sridhar, Richardson, TX (US);

Simon John Molloy, Allentown, PA (US);

Satoshi Suzuki, Ibaraki, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/7834 (2013.01);
Abstract

A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.


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