The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Sep. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Koushik Banerjee, Milpitas, CA (US);

Lu Liu, Boise, ID (US);

Sanjay Rangan, Boise, ID (US);

Enrico Varesi, Santa Clara, CA (US);

Innocenzo Tortorelli, Santa Clara, CA (US);

Hongmei Wang, Santa Clara, CA (US);

Mattia Boniardi, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 13/00 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0634 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 12/02 (2013.01); G06F 12/0238 (2013.01); G11C 13/0004 (2013.01); G11C 13/0023 (2013.01);
Abstract

One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.


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