The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Dec. 24, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sujit Sharan, Chandler, AZ (US);

Ravindranath Mahajan, Chandler, AZ (US);

Stefan Rusu, Sunnyvale, CA (US);

Donald S. Gardner, Los Altos, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/48 (2006.01); H01L 25/16 (2006.01); H01L 49/02 (2006.01); H01L 23/538 (2006.01); H01L 23/522 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 23/481 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 25/16 (2013.01); H01L 28/00 (2013.01); H01L 23/5384 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01);
Abstract

Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.


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