The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Mar. 14, 2018
Applicant:

Ibiden Co., Ltd., Ogaki, JP;

Inventors:

Toshiki Furutani, Ogaki, JP;

Takema Adachi, Ogaki, JP;

Toshihide Makino, Ogaki, JP;

Hidetoshi Noguchi, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01); H05K 3/18 (2006.01); H05K 3/06 (2006.01); H05K 3/24 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 3/14 (2006.01);
U.S. Cl.
CPC ...
H05K 1/113 (2013.01); H05K 1/0206 (2013.01); H05K 3/061 (2013.01); H05K 3/18 (2013.01); H05K 3/24 (2013.01); H05K 3/424 (2013.01); H05K 3/429 (2013.01); H05K 3/4682 (2013.01); H05K 1/0373 (2013.01); H05K 3/14 (2013.01); H05K 2201/09827 (2013.01); H05K 2203/0152 (2013.01); H05K 2203/0278 (2013.01); H05K 2203/0307 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/107 (2013.01);
Abstract

A printed wiring board includes a first conductor layer forming an inner conductor layer, a second conductor layer forming a first outemiost conductor layer, a third conductor layer forming a second outermost conductor layer, insulating layers including first and second insulating layers, first via conductors connecting the first and second conductor layers, and second via conductors connecting the first and third conductor layers. The first conductor layer has thickness greater than thicknesses of the second and third conductor layers, the second conductor layer includes component mounting pads positioned to mount an electronic component on the second conductor layer and extending outside component mounting region corresponding to projection region of the component, and the first via conductors include a first set of the first via conductors formed directly underneath the component mounting region and a second set of the first via conductors formed on outer side of the component mounting region.


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