The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2019
Filed:
Sep. 30, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Aliasgar S. Madraswala, Folsom, CA (US);
Kristopher H. Gaewsky, El Dorado Hills, CA (US);
Bharat M. Pathak, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/06 (2006.01); G11C 16/20 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0646 (2013.01); G11C 11/5628 (2013.01); G11C 16/20 (2013.01); G11C 16/3459 (2013.01); G06F 12/0246 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/2022 (2013.01); G11C 16/0483 (2013.01);
Abstract
In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory device comprising a plurality of NAND flash memory units. The storage device is to determine that the NAND flash memory device did not pass an initialization procedure; identify a first addressing scheme that is implemented by one or more of the NAND flash memory units that initialized properly; and after the initialization procedure, instruct each of the plurality of NAND flash memory units to implement the first addressing scheme.