The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2019

Filed:

Mar. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ren Wang, Portland, OR (US);

Yipeng Wang, Beaverton, OR (US);

Jr-Shian Tsai, Portland, OR (US);

Andrew Herdrich, Hillsboro, OR (US);

Tsung-Yuan Tai, Portland, OR (US);

Niall McDonnell, Limerick, IE;

Stephen Van Doren, Portland, OR (US);

David Sonnier, Austin, TX (US);

Debra Bernstein, Sudbury, MA (US);

Hugh Wilkinson, Newton, MA (US);

Narender Vangati, Austin, TX (US);

Stephen Miller, Round Rock, TX (US);

Gage Eads, Austin, TX (US);

Andrew Cunningham, Ennis, IE;

Jonathan Kenny, Co. Tipperary, IE;

Bruce Richardson, Sixmilebridge, IE;

William Burroughs, Macungie, PA (US);

Joseph Hasting, Orefield, PA (US);

An Yan, Orefield, PA (US);

James Clee, Orefield, PA (US);

Te Ma, Allentown, PA (US);

Jerry Pirog, Easton, PA (US);

Jamison Whitesell, Bethlehem, PA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/24 (2006.01); G06F 13/36 (2006.01); G06F 13/40 (2006.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 13/36 (2013.01); G06F 12/1027 (2013.01); G06F 13/24 (2013.01); G06F 13/4004 (2013.01); G06F 2212/50 (2013.01); G06F 2212/68 (2013.01);
Abstract

Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.


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