The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Dec. 27, 2017
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventors:

Chien-Cheng Tsai, Kaohsiung, TW;

Feng-Ming Huang, Pingtung County, TW;

Ying-Chiao Wang, Changhua County, TW;

Chien-Ting Ho, Taichung, TW;

Li-Wei Feng, Kaohsiung, TW;

Tsung-Ying Tsai, Kaohsiung, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10894 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02595 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first buried gate and a second buried gate in the substrate on the memory region; forming a first silicon layer on the substrate on the periphery region; forming a stacked layer on the first silicon layer; forming an epitaxial layer on the substrate between the first buried gate and the second buried gate; and forming a second silicon layer on the epitaxial layer on the memory region and the stacked layer on the periphery region.


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