The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Mar. 05, 2018
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

David Pritchard, Glenville, NY (US);

Lixia Lei, Clifton Park, NY (US);

Deniz E. Civay, Clifton Park, NY (US);

Scott D. Luning, Albany, NY (US);

Neha Nayyar, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/49 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/823418 (2013.01); H01L 21/84 (2013.01); H01L 29/0649 (2013.01); H01L 29/401 (2013.01); H01L 29/41783 (2013.01); H01L 29/4916 (2013.01); H01L 29/7838 (2013.01);
Abstract

Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.


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