The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Apr. 01, 2016
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Jun-Jie Wang, Changhua County, TW;
Yu-Lin Wang, Taipei, TW;
Tzu-Feng Chang, Pingtung County, TW;
Wei-Chi Lee, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/02 (2006.01); G03F 1/36 (2012.01); G11C 11/419 (2006.01); G11C 11/412 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G03F 1/36 (2013.01); G06F 17/5068 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01); H01L 27/1104 (2013.01);
Abstract
A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.