The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Oct. 25, 2017
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chun-Han Tsao, New Taipei, TW;
Chii-Ming Wu, Taipei, TW;
Cheng-Yuan Tsai, Chu-Pei, TW;
Yi-Huan Chen, Hsin Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method for manufacturing multi-voltage devices is provided. The method includes forming a pair of logic gate stacks in a logic region of a semiconductor substrate and a pair of device gate stacks in a multi-voltage device region. The pair of logic gate stacks and the pair of device gate stacks include first dummy gate material. The pair of device gate stacks also includes a work function tuning layer. The method further includes depositing second dummy gate material over the pair of logic gate stacks. The first dummy gate material and the second dummy gate material from over a first logic gate stack of the pair of logic gate stacks are replaced with an n-type material. The first dummy gate material and the second dummy gate material from over a second logic gate stack of the pair of logic gate stacks are replaced with a p-type material.