The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Nov. 21, 2013
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Chih-Chieh Chiu, Hsinchu, TW;
Chia-En Huang, Xinfeng Township, TW;
Fu-An Wu, Hsinchu, TW;
I-Han Huang, Tainan, TW;
Jung-Ping Yang, Jhi-bei, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/10 (2006.01); G11C 7/02 (2006.01); G11C 8/14 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 8/10 (2013.01); G11C 7/02 (2013.01); G11C 8/14 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract
An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells.