The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2019
Filed:
Feb. 15, 2017
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Trinh Hai Dang, Hsinchu, TW;
Hsing-Lien Lin, Hsin-Chu, TW;
Kai-Wen Cheng, Taichung, TW;
Cheng-Yuan Tsai, Chu-Pei, TW;
Chia-Shiung Tsai, Hsin-Chu, TW;
Ru-Liang Lee, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.