The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2019
Filed:
Jun. 20, 2016
SK Hynix Inc., Gyeonggi-do, KR;
Toshiba Memory Corporation, Tokyo, JP;
Jong-Koo Lim, Gyeonggi-do, KR;
Won-Joon Choi, Gyeonggi-do, KR;
Guk-Cheon Kim, Gyeonggi-do, KR;
Yang-Kon Kim, Gyeonggi-do, KR;
Ku-Youl Jung, Gyeonggi-do, KR;
Toshihiko Nagase, Tokyo, JP;
Youngmin Eeh, Tokyo, JP;
Daisuke Watanabe, Tokyo, JP;
Kazuya Sawada, Tokyo, JP;
Makoto Nagamine, Tokyo, JP;
SK Hynix Inc., Gyeonggi-do, KR;
TOSHIBA MEMORY CORPORATION, Tokyo, JP;
Abstract
Provided is a method for fabricating an electronic device including a variable resistance element which includes a free layer formed over a substrate and having a changeable magnetization direction, a pinned layer having a pinned magnetization direction, a tunnel barrier layer interposed between the free layer and the pinned layer, and a magnetic correction layer suitable for reducing the influence of a stray field generated by the pinned layer. The method may include: cooling the substrate; and forming the magnetic correction layer over the cooled substrate.