The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2019
Filed:
Oct. 25, 2016
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Tsung-Hsien Huang, Hsinchu, TW;
Hong-Chen Cheng, Hsinchu, TW;
Cheng Hung Lee, Hsinchu, TW;
Hung-Jen Liao, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01); H01L 23/522 (2006.01); G11C 7/18 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1128 (2013.01); G11C 7/18 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/0688 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.