The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Mar. 07, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventors:

Ying-Chiao Wang, Changhua County, TW;

Li-Wei Feng, Kaohsiung, TW;

Chien-Ting Ho, Taichung, TW;

Tsung-Ying Tsai, Kaohsiung, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10894 (2013.01); H01L 21/76224 (2013.01); H01L 27/10805 (2013.01); H01L 27/10814 (2013.01); H01L 27/10823 (2013.01); H01L 27/10885 (2013.01); H01L 27/10897 (2013.01); H01L 29/0649 (2013.01);
Abstract

A semiconductor memory device and a method of forming the same, the semiconductor memory device includes a substrate, a plurality of bit lines, a gate, a spacer layer and a first spacer. The substrate has a memory cell region and a periphery region, the a plurality of bit lines are disposed on the substrate, within the memory cell region, and the gate is disposed on the substrate, within the periphery. The spacer layer covers the bit lines and a sidewall of the gate. The first spacer is disposed at two sides of the gate, covers on the spacer layer.


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