The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Feb. 16, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chih-Wei Chiang, Zhubei, TW;

Po-Hsiung Leu, Taoyuan, TW;

Ding-I Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/82 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/82345 (2013.01); H01L 21/823431 (2013.01); H01L 21/823456 (2013.01); H01L 21/823462 (2013.01); H01L 21/823468 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 29/42364 (2013.01); H01L 29/4983 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01);
Abstract

The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate layer over the first portion and the second portion of the protection layer. The method for forming a semiconductor structure further includes patterning the dummy gate layer to form a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer.


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